Robust Design of Noise Tolerant 2-Phase Non Overlapping Clock Generating Circuit

This paper presents a circuit level technique for designing a robust 2-phase non overlapping clock generating circuit. The proposed 2-phase non overlapping clock generating circuit is simulated with Monte Carlo simulation sweep of 5000 and at a frequency of 1.5 GHz. An extensive simulation of the proposed circuit is performed using 16-nm high performance predictive technology mode (PTM) on SPICE platform. The proposed technique is observed to have high average noise threshold energy (ANTE) compared to the conventional circuit by a factor of 1.43X and also mitigating the impact of process, voltage and temperature variations, on various design parameters such as propagation delay, average power and power-delay product. The proposed circuit exhibits an improved noise characteristics and variability compared to the conventional circuit by using a 4-transistor based Schmitt trigger in place of inverters.