Contents Introduction
As it has been widely reported [1][2][3], MOSFET mismatch is related to the fluctuations of physical parameters such as oxide and interface charges or interface states, but its main cause is likely the random distribution of channel dopant number. Nevertheless, the experimental results, which have been published for a broad range of CMOS technology, do not quantitatively agree with theory. Analytical models which take into account the statistical fluctuations of the dopant number in the channel depletion layer [1][2] predict threshold voltage mismatch parameter (see Eq. 1 and Eq. 2) around for a technology, whereas experimental data fall in the range in the better cases [4][5] for a oxide thickness. As the difference between theory and experiment does not depend on device dimensions, this discrepancy could originate either from the channel dopant statistical distribution or from the polycrystalline silicon gate contribution. For example, it has been shown that threshold voltage fluctuations were related to the structure and the activation temperature of the gate especially in terms of depletion and dopant nonuniformity [6][7].
