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Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 /spl mu/m CMOS technology | IEEE Conference Publication | IEEE Xplore

Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 /spl mu/m CMOS technology


Abstract:

Matching characterization has been performed on 0.18 /spl mu/m NMOS devices for different substrate voltage values V/sub b/ and for various oxide thicknesses T/sub ox/, i...Show More

Abstract:

Matching characterization has been performed on 0.18 /spl mu/m NMOS devices for different substrate voltage values V/sub b/ and for various oxide thicknesses T/sub ox/, in order to determine the origin of the difference between experimental results and matching theory. Both experimental results and simulations outline an obvious tendency of mismatch to increase with T/sub ox/ and V/sub b/. Moreover, the greater contribution of threshold voltage mismatch seems to originate from the statistical fluctuations of channel dopant number. Nevertheless, Poisson distribution of channel dopant number fluctuations does not explain the absolute amplitude of threshold voltage mismatch that could be either related to channel dopant clustering or to deviation from Poisson statistical law.
Date of Conference: 19-22 March 2001
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-6511-9
Conference Location: Kobe, Japan

Introduction

As it has been widely reported [1][2][3], MOSFET mismatch is related to the fluctuations of physical parameters such as oxide and interface charges or interface states, but its main cause is likely the random distribution of channel dopant number. Nevertheless, the experimental results, which have been published for a broad range of CMOS technology, do not quantitatively agree with theory. Analytical models which take into account the statistical fluctuations of the dopant number in the channel depletion layer [1][2] predict threshold voltage mismatch parameter (see Eq. 1 and Eq. 2) around for a technology, whereas experimental data fall in the range in the better cases [4][5] for a oxide thickness. As the difference between theory and experiment does not depend on device dimensions, this discrepancy could originate either from the channel dopant statistical distribution or from the polycrystalline silicon gate contribution. For example, it has been shown that threshold voltage fluctuations were related to the structure and the activation temperature of the gate especially in terms of depletion and dopant nonuniformity [6][7].

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References

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