A Reconfigurable Arithmetic ADC for FPGA Implementations

This paper presents an Arithmetic ADC implementation for FPGAs, which is based on a minimum amount of external components. The basic design reuses the LVDS receiver of a FPGA IO interface as analog comparator, which is connected in feedback configuration via a R2R scaling network. Thus, a reference signal is converted from the digital domain to the analog domain and compared by the comparator. The application of the reference voltage by digital operations allows a wide functionality and enables reconfiguration. A clock synchronous digital design and the PVT robustness for a scaled references offers the portability to any FPGA platform. The wide range for possible reconfigurations is evaluated by common ADC topologies based on Digital Ramp ADC, Tracking ADC and SAR ADC. In order to demonstrate the high adaptability of the concept to application specific areas the conventional tracking scheme was extended by arithmetic operations. Due to this approach the results of the dynamic performance achieves an ENOB of 7.5 bit for a 8 bit system. The application of digital signal processing based on moving average filter methods improves the static performance due to error correction. Thus, the dynamic performance results in an ENOB of 10.4 bit. In summary, the arithmetic ADC system presented offers a high degree of functionality and reconfigurability, which can be applied to any FPGA platform.