Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics

Extraction method of process variation is proposed. Process monitor circuits are widely used for the extraction of process variation, however adding special purpose circuit increase the silicon area. Usually, silicon chips are tested electrically and functionally after the fabrication. IDDQ test is an electrical test which measures leakage current and find the fault in the target chip. Scan-test is a functional test which inputs and measures the internal signal vector using scan-flip-flop. We propose to an extraction method of process variation utilizing IDDQ test and retention characteristics of scan-flip-flop. This method enables process variation extraction without any extra process monitor circuit. Test structures are implemented into silicon chips and result shows global variation shift is extracted as threshold voltage shift.