Hardware Implementation of High Speed Bartlett Spectral Density Estimator Based on R4MDC FFT

Power spectrum analysis is a crucial matter in signal processing. In communication and biomedical signal processing, designing appropriate custom hardware for estimating signal is under everyday research. High frequency power spectrum estimator with embedded systems capabilities and for biomedical applications is the purpose of the current research. Nonparametric power spectral density estimation is the approach of this research in which no specific model is assumed in prior. This paper proposes a low power, high speed hardware with 125 MHz clock frequency rate, which its fast Fourier transform (FFT) engine is implemented with a radix-4 MDC structure. Bartlett method has been implemented in this research. The Artix-7 is the utilized FPGA in this research and VHDL is the used hardware design language. The proposed design computes Bartlett Power Spectral Density (PSD) estimation with only two added hardware units to a modified FFT engine. The offered limited power hardware performs well in small Word Length and high clock frequency.