A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs

The linearity of charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) is affected by systematic mismatch in its capacitor array. Fabrication phenomena, such as copper dishing, lead to radial gradients in the array, and the detrimental effect of these gradients cannot be mitigated by the use of common centroid layout techniques. In this work, a technique that uses the foreknowledge of radial gradients in order to shape the linearity of data converters is introduced. By choosing the order in which the capacitors within the physical array are connected during a conversion, it is possible to manipulate the converter linearity, and several integral nonlinearities (INLs) shapes can be obtained. This technique, also applicable for any ADC where the static linearity depends upon the mismatch within an array of regularly-placed circuit elements, has been successfully tested for a 10-bit SAR ADC implemented in a 180-nm CMOS process.