A 68μW 31kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10× compared to prior-art. A 0.18μm CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM
_S
of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm
²
area requirement.