First-Order Piezoresistive Coefficients of Lateral NMOS FETs on 4H Silicon Carbide

Stress dependent properties and modeling of lateral enhancement-mode NMOS FETS on 4H silicon carbide are described in detail for a wide range of bias conditions. NFET stress response is shown to include a strong threshold voltage component in addition to the expected mobility component, and a theoretical model for the stress dependencies closely matches the measured data. Values of the longitudinal and transverse piezoresistive coefficients are extracted from linear region measurements of the MOS transistors as a function of gate drive for the both crystallographic and chip coordinate systems. At low gate drive, threshold variations become much more important than the classic mobility terms, whereas high gate drive is utilized to extract the mobility terms from the data. Design of a four-transistor temperature compensated stress sensor rosette that requires a value of only one combined piezoresistive coefficient is also presented.