20.7 A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ

Driven by great demands for high data transfer rates in mobile communications, ADCs require wide bandwidths with low noise density and power consumption. The continuous-time ΔΣ modulator (CTDSM) is a suitable candidate for such applications as it has a simple slew rate requirement and inherently contains an anti-aliasing function. To satisfy the wide bandwidth (~100 MHz for LTE-A) and simultaneously maintain the energy efficiency of the CTDSM, a multi-bit quantizer (QTZ) is often utilized that relaxes the OSR, jitter and loop filter stability. On the other hand, new design issues, such as DAC nonlinearity and high power consumption in the data feedback and QTZ, rise with large numbers of bits in the QTZ. While the DAC mismatch can be suppressed by calibrations [1], [2] and the number of feedback DACs can be reduced to just one with feedforward [3] or QTZ-based excess loop delay (ELD) compensation [4], the QTZ design becomes the bottleneck in both the speed and resolution of the modulator. Here, we introduce a preliminary sampling and quantization (PSQ) technique that allows almost full utilization of a clock period for the quantization, thus leading to an extra 30% conversion time or an additional 12dB SQNR contribution when compared with the conventional approach. The modulator runs at 2GHz and attains 72.6dB SNDR and 76.3dB DR over a 100MHz bandwidth, while only consuming 16.36mW.