Computational Study of Geometrical Designs for Source/Drain Contacts to Reduce Parasitic Resistance in Extremely Scaled MOSFETs

Comprehensive simulation results are reported for the source/drain (S/D) geometry effects on the drive current of various n-type (Si, In
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Ga
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As, Ge) and p-type (Si, Ge) metal-oxide-semiconductor field-effect transistors (MOSFETs). Full-band Monte Carlo (MC) simulations are run for different S/D structures (“raised” versus “lateral”) at a relevant International Technology Roadmap on Semiconductors node (gate length 14 nm). The “lateral” S/D gives higher drive currents (lower parasitic resistance) than the “raised” S/D because carriers do not need to make large momentum changes through scattering to get injected into the channel or to get collected by the drain, unlike in the “raised” S/D where 90°-turns are required. The S/D geometry effect is significant for novel materials with light effective mass and low scattering rate (e.g., ~20% on-current change in In
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Ga
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As) while it is still not negligible (up to ~5%) for conventional Si. The effect is more pronounced with small contact resistivity and low-S/D doping density. The classical model (drift-diffusion) captures only a part of the S/D geometry effect. In MOSFET benchmarking for future technology nodes, it should be critical to consider the S/D structure effect using rigorous models (such as MC) to correctly project the drive current performance, especially for novel materials with high mobility.