A Bimodal (NRZ/PAM-4) ISI Tolerant Timing Recovery with Adaptive DDJ Equalization

This paper describes low latency bimodal NRZ/ PAM-4 timing recovery. This scheme reduces latency and power consumption by eliminating the need for data equalization in the timing recovery path for inter-symbol-interference limited channels. Rather it directly equalizes the data dependent jitter by adaptively shifting the ISI effected zero crossings. The implemented prototype in 65nm CMOS supports both 10 Gb/s NRZ and 20 Gb/s PAM-4 consuming only 23 mW. The CDR achieves more than f_baud/500 peaking free tracking bandwidth and adapts to optimized jitter tolerance for both PAM-4 and NRZ for the given input eye.