Fast QR Decomposition Based on FPGA

The QR-decomposition (QRD) is an implementation necessary for many different detection algorithms such as MIMO (Multiple Input and Multiple Output) in wireless communication system. In this article, a QRD processor which decomposes the matrix into an orthogonal (Q matrix) and upper triangular matrix (R matrix) using Gram Schmidt algorithm is designed and implemented using a 32-bit High speed processor based on FPGA. This design requires 16 clock cycle to compute QR decomposition with 15.625 M QRDs per second throughput at 250 MHz operating frequency.