Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic

One design technique that aims to reduce power consumption of MOS current mode logic dual-modulus frequency divider is presented in this paper. With combinational logic transferred the proposed scheme can obtain high working frequency. By merging the first master latches of CML DFFs, the simplified structure can achieve lower power consumption. Circuit simulation of the proposed structure in 28nm CMOS technology shows a 21% reduction of power consumption over conventional scheme is achieved at frequency of 56GHz.