Affirming Hardware Design Authenticity Using Fragile IP Watermarking

The increasing cost of IC fabrication and the ever-shrinking transistor size forces IC Industry to move its fabrication facilities to cheaper less reliable sources. This process creates the chance of inserting malicious manipulations namely Hardware Trojans at different phases of the design cycle. Trojans are a real challenge to IC industry especially in an era of smart cities and connected sensors. In this paper, we propose a behavioral fragile IP watermarking technique that embeds the signature in finite state machines (FSMs) transitions to ensure design integrity. The inserted fragile mark is extremely sensitive to any design alterations, which makes it an excellent and economical choice to detect design changes. Finally, we analyze and evaluate different aspects of the proposed technique, including sensitivity to design changes, robustness, as well as complexity and insertion overhead to design cycle.