Low-Latency Mapping Algorithm for Network-on-Chip

As a new generation of SoC design scheme, Network-on-Chip (NoC), is being adopted by more and more chips as communication architecture. In this paper, the N oC mapping problem is studied, and a low latency NoC mapping algorithm is proposed to reduce N oC communication latency in mapping specific applications to the N oC architecture. The algorithm reduces the communication latency by balancing the link load of the IP of NoC which associate the individual tasks. The experimental results show that the algorithm proposed in this paper reduces the execution time of N oC by 20 ~ 40% and 10%, respectively, compared with the sequential mapping and simulated annealing algorithm.