A microelectronic test structure for signal integrity characterization in deep submicron technology

The benefits expected by the decreases of feature sizes in high-speed electronic's circuits are limited by the increased parasitic effects of interconnect. This paper details the application of an on-chip time domain technique to the characterization of propagation delay, crosstalk and crosstalk-induced delay, along interconnects in deep submicron technology. The measurement system is detailed, together with the signal integrity patterns and their implementation in 0.18 CMOS technology. Measurement obtained with this technique are presented and compared with simulations.