A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

Junctionless transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of t
_si
from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted t
_si
values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.