Fault insertion software and hardware testing for safety PLC-based system SIL certification

Challenges and solutions related to Programmable Logic Controller (PLC) and PLC based Instrumentation and Control systems (PICS) verification and validation (V&V) are discussed. A particular case of safety critical PICS developed using FPGA (FPICS) is analyzed. Fault insertion testing (FIT) is one of the V&V techniques and FIT is applied to meet the IEC 61508 standard requirements and to be certified and confirm safety integrity level (SIL3). The concept of ability of SW and HW (as components of FPICS) to FIT (FIT-ability), some theoretical issues and procedures, specific features of FPICS SIL-certiflcation techniques are discussed. The suggested FIT techniques and tools are described basing on experience of SIL-certificating some modules of FPGA-based platform RadICS for NPP FPICS. Particularity of the technique is joint application of FIT for hardware (FPGA design) and software (VHDL code) considering FIT-ability issue.