Measurement of temperature effect on random telegraph noise induced delay fluctuation

We present detailed measurement results of temperature effect on Random Telegraph Noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On-Thin-Buried-Oxide process. Skewed ring oscillators (ROs) are used to characterize pMOFSET and nMOSFET specific RTN effects. Distributions of overall threshold fluctuation of a device have been extracted such that the simulated delay distribution matches with the measured delay distribution. For worst-case delay prediction, circuit analysis with Δν
τ
distribution model for low temperature is necessary. Estimation results reveal that RTN amplitude decreases slightly with the increase of temperature. However, low correlation of 0.3 to 0.4 has been observed across temperatures ranging from 0 °C to 80 °C for delay paths. We find appearing and disappearing of traps across the temperature range causing the low correlation. Low correlation poses challenges in realizing robust runtime performance compensation techniques such as replica critical path based delay compensation.