Tutorial T2B: Hardware Intellectual Property (IP) Security and Trust: Challenges and Solutions

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. In this tutorial, we plan to provide a comprehensive coverage of both fundamental concepts and recent advances in validation of security and trust of hardware IPs. It examines the state-of-the-art in research in this challenging area as well as industrial practice, and points to important gaps that need to be filled in order to develop a validation and debug flow to establish the necessary trust level of hardware IPs, eventually leading to secure SoC systems. The tutorial presenters with complementary areas of expertise and extensive experience of consulting for leading companies and R&D labs will provide a unique snapshot of the challenges, cutting-edge solutions and open problems in this area. The selection of topics covers a broad spectrum and will be of interest to a wide audience including design, validation, security, and debug engineers. The proposed tutorial consists of four parts. The first part introduces security vulnerabilities and various challenges associated with trust validation for hardware IPs. Part II covers various demonstrated attacks and design modification based countermeasures such as hardware watermarking and obfuscation. Part III covers formal methods, simulation-based approaches as well as side channel analysis for security and trust validation in hardware IPs. Finally, Part V concludes this tutorial with discussion on emerging issues and future directions.