Implementation of power estimation methodology for intellectual property at SoC level

In VLSI design flow, the designer has better control over critical parameters such as power consumption and delay at higher levels of abstraction. Trade-offs and design changes are easier to accomplish at architectural and system levels. The decisions taken at these levels have a large impact on the final quality of the design. Power consumption has become a vital issue in all modern designs. However, actual information on this important metric is available only after the back-end phase when the design is committed to silicon. At this juncture, very little can be done to optimize power. Therefore, power estimation at higher levels is an extremely crucial step in executing power aware designs. Power estimation techniques can be applied at all abstraction levels in the low power design flow, of which highest level is system level. The design process at higher abstraction level shields the designer's crucial time and effort in power estimation. It is challenging to extract and analyse knowledge about the circuit of the system at the system level. If we estimate the power at this level, large power savings can be done and also power optimized design changes can be done. This paper describes an augmented power estimation methodology for intellectual property (IP) components. The method uses statistical methods to isolate a set of input influencing the output power for a particular mode of operation. The power model is developed as a function of parameters such as signal probability, transition density and spatial correlation. The proposed method was evaluated on a SDRAM controller core. The power estimation error varies from 0.3% to 12.5%.