A dual-element VNA electronic calibration in CMOS

This paper presents a dual-element direct on-wafer VNA calibration algorithm using calibration standards fabricated in 65-nm CMOS technology. To solve for the seven unknowns in the two-port error models, the proposed algorithm utilizes a thru and a n structure where the later consists of three NMOS transistors whose impedances can be modulated independently through the corresponding gate bias. The algorithm is validated against on-wafer TRL with experimental results from 1 to 67 GHz. By minimizing the number of probe landings and calibration standards using CMOS technology, the presented approach shows potential for more accurate measurements at nanoscale transistor structures.