Design and Electrical Characterization of 2-T Thyristor RAM With Low Power Consumption

In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (
${T}_{\text {write}}$
) and erase time (
${T}_{\text {erase}}$
) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 10
⁵
. Also,
${V}_{\text {write}}$
and erase voltage (
${V}_{\text {erase}}$
) of the 2-T TRAM appear to be below 2 and −1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.