A 3.25 GS/s 4-Tap analog FIR filter design with coefficient control using 6-bit split-capacitor DAC as a tunable coefficient multiplier

A proof-of-concept bandwidth and notch frequency tunable 3.25 Gs/s 4-Tap analog FIR filter is presented. A 6-b Split-capacitor DAC is introduced as a reconfigurable coefficient multiplier for frequency response adjustment. The proposed AFIR filter has been implemented in a 32nm SOI CMOS. The filter achieves capability of 240 ~ 710 MHz low pass band tuning range and 0.54 ~ 1.625 GHz notch frequency tuning range based on post-layout simulations while maintaining high linearity (IIP3>11.3 dBm) and consuming low power (<;9.3 mW). The simulation results show a minimum SFDR of 42.7 dBc.