Energy Efficient Affine Register File for GPU Microarchitecture

As modern GPUs can accommodate thousands of hardware threads, each of which has its own dedicated register file for fast context switching, to achieve high throughput and performance, power consumption has become an important issue. It has been observed that many SIMD groups in GPU execute with the same input values and generate the same output values, and hence uniform/scalar register files of GPUs have been proposed to eliminate these redundant computations and memory accesses for these scalar executions. In this paper, we propose the affine register file design for GPUs to reduce the redundant executions as the input values are the uniform and affine patterns. We use a pair of registers, a base and a stride, to store affine vector and specific affine ALUs to execute affine instructions. Compiler performs analysis to detect the affine vectors and instructions and adds the annotations for these non-vector computations. Moreover, if the operation cannot keep the value in affine style, the compiler-helped hardware conversion mechanism will translate the affine vector into general vector. In Our evaluations, it shows that our design can reduce vector computation rate to 44.85% and 55.15% of computation rate dispatched to scalar and affine computation. Our design can also reduce approximately 66.84% energy consumption of register files, 38.67% energy consumption of ALUs and average 4.78% of total energy consumption of GPU.