PCB/IC Co-Design Concepts for SEED

The basis of the system efficient ESD design (SEED) concept is the characterization of IC pins regarding hard failures during system level ESD discharge. The methodology described essentially establishes the role of isolation design, but a realistic design should consider the full role of PCB elements and their respective frequency responses. The chapter describes the simulation procedure that should include the filtering responses from the board components. Most PCB designs implement on-board resistors and capacitors to achieve IEC protection. PCB design for system level protection is an art that the system designer commonly practices to achieve the level of desired protection. An optimum design should involve the ?>system efficient design.?> SEED requires an understanding of the interaction between the external TVS device and interfacing IC pin's transient behavior. The selected application-specific data transmission lines have to provide injection points where a directed pulse current can be forced.