Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects

The network-on-chip (NoC) has been introduced as an efficient communication backbone to tackle the increasing challenges of on-chip communication. Nevertheless, merely metal-based NoC implementation offers only limited performance and power scalability in terms of multicast and broadcast traffics. To meet scalability demands, this paper addresses the system-level challenges for intra-chip multicast communication in a proposed hybrid interconnects architecture. This hybrid NoC combines and utilizes both regular metal on-chip interconnects and new type of wireless-NoC (WiNoC) which is Zenneck surface wave interconnects (SWI). Moreover, this paper embeds novel multicast routing and arbitration schemes to address system-level multicast-challenges in the proposed architecture. Specifically, a design exploration of contention handling in SWI layer is considered in both centralized and decentralized manners. Consequently, the hybrid wire-SWI architecture avoids overloading the network, alleviates the formation of traffic hotspots and avoid deadlocks that are typically associated with state-of-the-art multicast handling. The evaluation is based on a cycle-accurate simulation and hardware description. It demonstrates the effectiveness of the proposed architecture in terms of power consumption (up to around 10x) and performance (around 22x) compared to regular NoCs. These results are achieved with negligible hardware overheads. This study explore promising potential of the proposed architecture for current and future NoC-based many-core processors.