Design metrics improvement of 10TSRAM cell using CNFET

This article presents a variability resilient CNFET based 10T S RAM cell. Critical design metrics of S RAM cells are estimated using Monte-Carlo simulations and compared with that of conventional Si-MOSFET based 10T S RAM cell. The CNFET based SRAM cell offers 3.15× and 1.98× improvements in Read Access Time (T
_RA
) and Write Access Time (T
_WA
) respectively. The proposed bit cell also offers 1.94× and 5.8× improvements in T
_RA
and T
_WA
variability respectively compared to its MOSFET counterpart. Moreover, our bit cell exhibits 39% higher read static noise margin (RSNM) and 7% higher write static noise margin @ 800 mV.