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A high density integrated test matrix of MOS transistors for matching study | IEEE Conference Publication | IEEE Xplore

A high density integrated test matrix of MOS transistors for matching study


Abstract:

This paper describes a test structure for the characterization of MOS transistor matching. It integrates (on 1.5 mm square) a matrix of 480 transistors to be tested, toge...Show More

Abstract:

This paper describes a test structure for the characterization of MOS transistor matching. It integrates (on 1.5 mm square) a matrix of 480 transistors to be tested, together with the analog switches and shift registers necessary for individual access to these transistors. This circuit has been integrated on an experimental fully depleted silicon on insulator (SOI) process as well as on a standard bulk process. Results for the SOI matching properties are discussed.
Date of Conference: 23-26 March 1998
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-4348-4
Conference Location: Kanazawa, Japan

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