A high density integrated test matrix of MOS transistors for matching study

This paper describes a test structure for the characterization of MOS transistor matching. It integrates (on 1.5 mm square) a matrix of 480 transistors to be tested, together with the analog switches and shift registers necessary for individual access to these transistors. This circuit has been integrated on an experimental fully depleted silicon on insulator (SOI) process as well as on a standard bulk process. Results for the SOI matching properties are discussed.