Abstract:
This paper describes a test structure for the characterization of MOS transistor matching. It integrates (on 1.5 mm square) a matrix of 480 transistors to be tested, toge...Show MoreMetadata
Abstract:
This paper describes a test structure for the characterization of MOS transistor matching. It integrates (on 1.5 mm square) a matrix of 480 transistors to be tested, together with the analog switches and shift registers necessary for individual access to these transistors. This circuit has been integrated on an experimental fully depleted silicon on insulator (SOI) process as well as on a standard bulk process. Results for the SOI matching properties are discussed.
Published in: ICMTS 1998. Proceedings of 1998 International Conference on Microelectronic Test Structures (Cat. No.98CH36157)
Date of Conference: 23-26 March 1998
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-4348-4
