A 40–50 GHz power amplifier with flat gain response in 90 nm CMOS technology

This paper presents a 40-50 GHz power amplifier (PA) with flat gain response using TSMC 90 nm CMOS technology. The PA is a three-stage design with a first stage single-ended amplifier to drive a two stage balanced amplifier. Cascode configuration is employed in each stage to provide high small-signal gain. A gain-boosting technique is introduced in the cascode configuration of the PA to extend high-frequency gain characteristics for gain flatness. Measured results show that the PA achieves a small-signal gain of 26 ± 1 dB from 40 to 50 GHz. The measured saturation output power (P
_sat
) is 16 dBm at 45 GHz with the power-added efficiency (PAE) of 12% and the output 1-dB compression point (OP
_1dB
) is 12.3 dBm.