A new technique for probing the energy distribution of positive charges in gate dielectric

To simulate the impact of stress-induced positive charges in gate dielectric on devices and circuits, it is essential to know their energy distribution both within and beyond substrate band-gap. A new technique is proposed for measuring this distribution and successfully implemented on industrial parameter analyzer. We demonstrate its generic applicability to both SiON and high-k/SiON stacks and its capability in evaluating different materials and processes. This makes it a useful tool in a typical test laboratory for material and process optimization.