TLM: a trench leakage monitor for a four megabit DRAM technology

An array of substrate-plate trench-capacitor dynamic random access memory (DRAM) cells is used for quantification of parasitic leakage mechanisms, silicon defects, and device parametrics. Parasitic devices aid process characterization, parametric cross-correlations, and technology/device design-point evaluation. Used in conjunction with a functional monitor, the trench leakage monitor, is found to be a valuable semiconductor process-development vehicle to achieve functionality and cell-retention yield for a 4-Mb DRAM CMOS technology.<>