Test structures and finite element models for chip stress and plastic package reliability

Failure modes induced by plastic package stress in multilayer metal-dielectric-passivation structures in large chips are investigated. An arrayable test chip is designed to contain representative metal-dielectric configurations that lend themselves to simple electrical measurement of stress-induced failures such as metal-to-metal leakage caused by interlayer dielectric cracking. Extensive data on the effects of chip size, distance from the corner, metal geometry, temperature cycling, and assembly variables are generated using the test chip. The failure modes are investigated using finite-element modeling (FEM). A modeling technique is used to address the problem of corner singularities, which is encountered in calculating shear stresses near chip corners. An approach is developed to derive die design rules using the accelerated failure rate data generated by the test chip in conjunction with the FEM stress curves. Some simple solutions to the package stress problem are demonstrated.<
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