Scalable thermal resistance model for single and multi-finger silicon-on-insulator MOSFETs

This paper presents a thermal resistance model for silicon-on-insulator MOSFETs. The proposed model accounts for various heat dissipation paths in the device accurately and is accurate for both multi and single finger devices. Model development is based on carefully designed test structures to account for different heat dissipations paths. Improvement in the drain current fits across devices when using proposed model over standard BSIMSOI4.3 validates the model.