Scalable Block-Based Parallel Lattice Reduction Algorithm for an SDR Baseband Processor

Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. In this paper the Scalable Block-based Parallel LR algorithm (SBP-LR) is proposed and optimized for parallel programmable baseband architectures offering ILP and DLP features. In our algorithm, architecture-friendliness is explicitly introduced from the very beginning of the algorithm/architecture co-design flow. In this context, abundant vector-parallelism is enabled with highly-regular and deterministic data-flow. Hence, SBP-LR can be easily parallelized and efficiently mapped on Software Defined Radio (SDR) baseband architectures. The proposed algorithm has been implemented on ADRES and is evaluated in the context of 3GPP LTE. Most of the previously reported algorithms are implemented for ASIC or FPGA. However, to the best of author's knowledge, this is the first reported LR algorithm explicitly optimized for a Coarse Grain Reconfigurable Array (CGRA) processor like ADRES.