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Test structure for mismatch characterization of MOS transistors in subthreshold regime | IEEE Conference Publication | IEEE Xplore

Test structure for mismatch characterization of MOS transistors in subthreshold regime


Abstract:

This paper proposes a simple test circuit for characterization of MOS transistor mismatch in a standard 2 /spl mu/m CMOS technology. Measurements have been performed both...Show More

Abstract:

This paper proposes a simple test circuit for characterization of MOS transistor mismatch in a standard 2 /spl mu/m CMOS technology. Measurements have been performed both in the saturation and subthreshold regimes in order to obtain an accurate characterization in a wide range of operations. The parameter mismatch estimation algorithm is based on Multiple Linear Regression and is able to furnish information on the estimation accuracy.
Date of Conference: 17-20 March 1997
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-3243-1
Conference Location: Monterey, CA, USA

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