Abstract:
This paper presents the measurement and characterization of multi-layered interconnect capacitances for a 0.35 /spl mu/m CMOS logic technology, which is becoming a critic...Show MoreMetadata
Abstract:
This paper presents the measurement and characterization of multi-layered interconnect capacitances for a 0.35 /spl mu/m CMOS logic technology, which is becoming a critical circuit limitation to high performance VLSI design. To measure multi-layered capacitances of interconnect lines, test structures and the measurement methodology are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies.
Date of Conference: 17-20 March 1997
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-3243-1