A design partitioning algorithm for Three Dimensional Integrated Circuits

Three Dimensional Integrated Circuits (3D ICs) are designed to have better performance and yield. Devices of a circuit are placed on different layers. Through-Silicon Vias (TSV) is used to connect a signal that crosses adjacent layers. In this paper we propose an algorithm to partition an integrated circuit with the objective to minimize the number of TSV and chip area. The advantages of lowering the number of TSV are not only reducing chip delay but also decreasing the area. Experimental results show that the program can partition a circuit with small number of TSVs in a short time. For the case of the largest test circuit with 85013 cells, after partitioning in to 5 layers, the number of TSV is only 142 and the average percentage of area overhead is only 0.1%. We achieve the best result, among all teams that participated in the 2009 IC/CAD contest in Taiwan.