Design of dual threshold voltages asynchronous circuits

This paper introduces a framework for the minimization of leakage power consumption of asynchronous circuits via using dual threshold voltages technique. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the circuit. We propose a heuristic method based on quantum genetic algorithm which finds the optimal high and low threshold voltage assignment. Experimental results are given for a number of 90 nm ISCAS benchmark circuits. From the experimental results, we show that the combination of asynchronous and multiple threshold voltage design techniques is an effective way to achieve low leakage power budget in high performance asynchronous circuits.