Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs

Heat removal technologies are among the most critical needs for 3D integration of high-performance microprocessors. As high performance chips are projected to dissipate more than 100W/cm
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and require more than 100A of supply current, integrating high performance chips in a 3D stack greatly exacerbates challenges in power delivery and cooling of chips within the stack. This paper reports the configuration of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for 3D architectures with integrated high-performance processors in the 3D stack. The researchers demonstrate the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. The on-chip integrated microchannel heat sinks enable cooling of >100W/cm
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of each high power density chip. A key element in this platform is the ability to assemble chips with electrical and fluidic I/Os and seal fluidic interconnections at each strata interface. Three assembly and fluidic sealing techniques are discussed. Fabrication, assembly, and experimental results of the novel fluidic sealing technologies that enable the microfluidic network in the inter-layer liquid cooling 3D integration platform are also reported.