Combined test structure for systematic and stochastic mosfets and gate resistance process variation assessment | IEEE Conference Publication | IEEE Xplore

Combined test structure for systematic and stochastic mosfets and gate resistance process variation assessment


Abstract:

A powerful and compact test structure based on the combination of mosfet and resistor mismatch-like configurations is presented. This new combined solution helps to asses...Show More

Abstract:

A powerful and compact test structure based on the combination of mosfet and resistor mismatch-like configurations is presented. This new combined solution helps to assess not only the systematic and stochastic mosfet and gate resistance electrical performance and their process variations but also the dependencies on the environment and the impact of different layout solutions.
Date of Conference: 22-25 March 2010
Date Added to IEEE Xplore: 20 May 2010
ISBN Information:

ISSN Information:

Conference Location: Hiroshima, Japan

Contact IEEE to Subscribe

References

References is not available for this document.