On matching properties and process factors for submicrometer CMOS

Matching property of a 0.5 /spl mu/m CMOS process is investigated. Short channel effect in matching is studied by incorporating source and drain parasitic resistance, which contributes significantly to high-gate-bias mismatch. In characterizing matching statistics, it is found that long-spacing mismatch, due to process gradients, differs considerably from short-spacing mismatch. Threshold voltage mismatch is proportional to (WL)/sup -0.75/ due to local edge variations. In addition, a n/sup 0.5/-law model is developed to model the stripe-layout mismatch.