A 10Gb/s CMOS Clock and Data Recovery Circuit with a HalfRate Linear Phase Detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-µm CMOS technology in an area of 1.1 x 0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28 x 10^-6, with random data input of length 2²³ - 1. The power dissipation is 72 mW from a 2.5-V supply.