A novel calibration technique applying to an adaptive-bandwidth PLL

This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL. The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly. The maximum calibration time is less than five comparison periods. With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole working range. The proposed circuit has been implemented in 0.18um CMOS logic process. Results show that the calibration time is less than 1.2μs, and the total locking time is less than 3μs. The PLL has good jitter performance within its operating range from 860MHz to 2.1GHz.