Comprehensive study of bias temperature instability on polycrystalline silicon thin-film transistors

The negative and positive bias temperature instabilities are investigated on p-channel and n-channel TFTs with four different combinations. The stress-induced hump in the subthreshold region is observed for PBTI on p-channel TFTs and NBTI on n-channel TFTs. The hump is attributed to the edge transistors along the channel width direction. Higher electric field at the corners induces more trapped carriers in the insulator as compared to channel transistor. In contrast, no humps are observed for NBTI on p-channel TFTs and PBTI on n-channel TFTs. For NBTI on p-channel TFTs, the interface traps are generated by breaking the Si-H bonds and are responsible for the negative ¿V
_T
. On the other hand, electrons are trapped in the insulator and induce positive ¿V
_T
for PBTI on n-channel TFTs.