Abstract:
The authors describe the experimental procedures necessary to obtain the different parameters for a SPICE II VDMOS model, emphasizing the influence of the load resistance...Show MoreMetadata
Abstract:
The authors describe the experimental procedures necessary to obtain the different parameters for a SPICE II VDMOS model, emphasizing the influence of the load resistance on the capacitive parameter extraction from a current analysis in the transient mode. These techniques have been applied to different fabricated interdigitated VDMOS structures, and good agreement has been obtained between SPICE II simulations and experimental data. The influence of a two-level gate oxide on the switching times is investigated.<>
Date of Conference: 13-14 March 1989
Date Added to IEEE Xplore: 27 June 2005
Print ISBN:0-87942-714-0