A test structure of a MOSFET with Si-implanted gate-SiO/sub 2/ for EEPROM applications

The C-V and I-V characteristics of an n-MOSFET with Si-implanted gate-SiO/sub 2/ of 50 nm are analyzed by using a test device with large equal channel width and length of 100 /spl mu/m, and discussed for realizing a large hysteresis window of threshold voltage. Interface trap densities change logarithmically from /spl sim/3/spl times/10/sup 10/ to /spl sim/1/spl times/10/sup 12/ cm/sup -2/ eV/sup -1/ as the Si-dose at 25 keV increases from zero to 3/spl times/10/sup 16/ cm/sup -2/. Threshold-voltage changes caused by 25 keV implantations are as high as /spl plusmn/0.2 V. Effective mobilities (subthreshold swings) change from /spl sim/600 (/spl sim/0.10) to /spl sim/100 cm/sup 2V/spl middot/s (/spl sim/0.26 V/decade) as the Si-dose increases from 0 to 3/spl times/10/sup 16/ cm/sup -2/ at 25 keV, and both parameters are related with the change of interface trap densities. There is a close relationship between the hysteresis windows of gate current and threshold voltage, and the largest threshold voltage window in a low gate voltage region is obtained for the MOSFET with Si-implantation at 25 keV/3/spl times/10/sup 16/ cm/sup 3/.<
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