Yield enhancement in the routing phase of integrated circuit layout synthesis

An algorithm for integrated circuit yield enhancement in the routing phase of layout synthesis is proposed. The focus is on detailed routing. The proposed algorithm reduces layout critical area for short circuits. Critical area reduction is achieved without any penalties on net length. The defect tolerant features of the algorithm include efficient net merging and final track assignment aimed toward critical area reduction. The proposed algorithm overcomes the limitations associated with the existing defect tolerant routing algorithms.<>