The inverter matrix: a vehicle for assessing process quality through inverter parameter analysis of variance

An inverter matrix has been fabricated in 1.6- mu m CMOS which allows for a large ( approximately=500) number of inverters to be characterized by a single 2*10 pad array test structure. The variance of the inverter threshold voltage can be expressed as a function of inverter geometry and MOSFET threshold voltages. The standard deviation of the inverter threshold voltage has been observed to be as small as 2.3 mV within a matrix. The inverter matrix is proposed as a standard evaluation circuit for assessing process quality.<
>