Substrate isolation in 0.18um CMOS technology

Various methods of substrate isolation in a typical 0.18 /spl mu/m CMOS process technology, with and without deep nwell (DNW), have been studied. Results are presented on the impacts of guard ring, substrate contact size and proximity, and DNW at various biases on isolation. |S21| is used as a measure of isolation. An N+ to Psub junction diode is used as both the source of noise injected into the substrate and as the sensor for noise pick up. It is shown that isolation based on DNW works well up to several Gigahertz, but at higher frequencies the impacts of P+ guard ring and DNW are about the same in reducing the substrate coupling. It is also shown that the impact of DNW on substrate isolation is comparable with published results for SOI.